1. Field of the Invention
The present invention relates generally to a multi-input transistor and a multi-input transcondutor circuit and, more particularly, to a multi-input transistor and a multi-input transconductor circuit tliat are suited to a signal processing system.
2. Description of the Related Background Art
A multi-input element having a plurality of inputs is employed in a variety of fields ranging from an analog/digital mixing signal processor for performing not only a simple logic operation and a comparison but also a multiplication and an addition. In such a mixing signal processor, it is desired that ratio of the gains between any inputs and outputs should be realized with high accuracy. A transconductor circuit capable of obtaining a current output with respect to a plurality of voltage inputs responds to such a demand. Further, as one example of the multi-input element, there has hitherto been employed a pseudo multi-input MOS transistor (hereinafter simply termed a multi-input MOS transistor) for causing the MOS transistors to operate as if a single MOS transistor having a multiplicity of inputs operates by combining the MOS transistors. This is also one example of the transconductor circuit.
The conventional multi-input transconductor circuit proposed is actualized typically by connecting a plurality of single-unit transconductors in parallel.
A known single transconductor circuit is disclosed in, e.g., U.S. Pat. No. 4,749,957. The transconductor circuit in which the plurality of transconductors are connected in parallel is stated in, e.g., "A Versatile Building Block: The CMOS Differential Amplifier" written by Saeckinger and Guggenbuehl, IEEE Semiconductor Circuit Journal, Vol.22, No. 20, April 1987, wherein a plurality of differential amplifiers having absolutely the same configuration are disposed in parallel. FIG. 11 illustrates such an example. In this example, the transconductor circuit includes a first differential amplifier constructed of two N-channel MOS transistors Q1, Q2 having gates to which voltages V.sub.PP, V.sub.PN are respectively applied and sources common-connected and thus connected to a current source. This transconductor circuit also includes a second differential amplifier constructed of two N-channel MOS transistors Q3, Q4 having gates to which voltages V.sub.NP, V.sub.NN are respectively applied and sources common-connected and thus connected to a current source. The drains, on the correis sponding side, of the transistors Q1, Q4 and the transistors Q2, Q3 are common-connected. An output current io is obtained from the drain side of the transistor Q4.
According to the above-mentioned construction, however, the current output does not bear a proportional relationship with the input voltage, with the result that a linearity is not obtained. This is not suited to the signal processor system.
Furthermore, U.S. Pat. No. 4,533,867 discloses a two-input transconductor, wherein there is proposed an actualization of a feedback loop for consecutively adjusting an output common voltage level of the differential amplifier. There arises, however, a problem inherent in the transconductor disclosed therein, the problem being such that mutual conductances do not coincide due to a difference in threshold voltage between the transistors constituting the circuit. For this reason, a capability of dealing with the signals is restricted, and the transconductor has only a small dynamic range.